Conference Publication

  1. SREE RANJANI R, Sree Ranjani R, and Nirmala Devi M,"Online monitoring based Design-for-Trust technique to build a Trusted Hardware Design", 32nd International Conference on VLSI Design (PhD Forum). ,Delhi, 2019.
  2. SREE RANJANI R, Sree Ranjani R,,"Secured Hardware Design against Trojans at Gate-Level Netlist", 32nd International Conference on VLSI Design (User Design Contest). ,Delhi, 2019.
  3. SREE RANJANI R, Sree Ranjani R, and Nirmala Devi M,"A Novel Logical Locking Technique against key-guessing attacks", 8th International Symposium on Embedded computing and system Design (ISED’2018). ,CUSAT University, 2018.
  4. SREE RANJANI R, Nirmala Devi M,"Enhanced Logical Locking for a Secured Hardware IP against Key-guessing Attacks", 22nd International symposium on VLSI Design and Test (VDAT),MADURAI, 2018.
  5. SREE RANJANI R, T. Saran and Nirmala Devi M,"A region based fingerprinting for hardware trojan detection and diagnosis", 4th International Conference on Signal Processing and Integrated Networks (SPIN),AMITY UNIVERSITY, 2017.
  6. SREE RANJANI R, Nirmala Devi M,"Golden-chip Free HT Detection and Diagnosis Using Power Signature Analysis", 7th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT),ITC SONAR, KOLKATTA, 2016.
  7. SREE RANJANI R, et.al.,,"Low Power Full Adder with Reduced Number of Transistor", National Conference on Innovations in Electronics, Communication & Network Technologies, NCIECNT’14, , 2014.
  8. SREE RANJANI R, et.al.,,"Reduction of Capture and Launch power in VLSI Testing", National Conference on Innovations in Electronics, Communication & Network Technologies, NCIECNT’14, , 2014.
  9. SREE RANJANI R, et.al.,,"A Built-In Repair Analyzer With Improved Optimal Repair Rate For 64-Bit Oriented Memories", International conference on recent innovations in Engineering, , 2014.
  10. SREE RANJANI R, et.al.,,"A Built-In Repair Analyzer With Optimal Repair Rate For 64-Bit Oriented Memories", 4th International conference on Advanced computing, control systems, machines and embedded technology” ICACT2014,J.K.K.Nattraja college of Engineering and Technology , 2014.
  11. SREE RANJANI R, Pushpa Latha,"Design and implementation of ALU using low power 8T full adder & MUX", 8th National Conference on innovations in Communication and Computing NCICC’13, , 2013.
  12. SREE RANJANI R, Meenaakshi Sundhari,"Design of low power ALU", International conference on computing technologies, embedded system and drives, , 2012.
  13. SREE RANJANI R, Meenaakshi Sundhari,"Design of low power ALU with 10T full adder", 2nd National Conference on Computing, Communication and devices (NCCCD’12), , 2012.
  14. SREE RANJANI R, Meenaakshi Sundhari,"Design Of High Speed Low Power Arithmetic Logic Unit", (NCVCC’12) National Conference on VLSI, Communication & Computation, , 2012.
  15. SREE RANJANI R, Meenaakshi Sundhari,"High speed low power arithmetic & logic unit design", 1st National Conference on Emerging Technologies in advanced communication system (NCETACS’12, , 2011.